Microchip has released a new DeviceDoc for the PIC32MZ Graphics (DA) Family Datasheet of devices.Description of Change: This revision includes the following major changes, which are referenced by their respective chapter in Table A-5. In addition, minor updates to text and formatting were incorporated throughout the document. 1.0 Device Overview The PIC32MZ DA Family Block Diagram was updated (see Figure 1-1). The 176-pin LQFP pin number for SDA3 in the I1C1 through I2C5 Pinout I/O Descriptions was updated (see Table 1-10). The 169-pin LFBGA pin numbers for EBIOE and EBIWE in the EBI Pinout I/O Descriptions were updated (see Table 1-13). 2.0 Guidelines for Getting Started with 32-bit Microcontrollers The following sections were added: 2.7.1 Crystal Oscillator Design Consideration 2.9 Considerations When Interfacing to Remotely Powered Circuits 4.0 Memory Organization The PIC32MZ DA Family Memory Map was updated (see Figure 4-1). 10.0 Direct Memory Access (DMA) Controller CRCTYP bit number references in the DMA CRC Control Register were updated (see Register 10-4, Register 10-5, and Register 10-6). 36.0 Graphics LCD (GLCD) Controller The key features for the module were updated. 37.0 2-D Graphics Processing Unit (GPU)The key features for the module were updated. The GPURESET bit reference in Note 2 was updated. 38.0 DDR2 SDRAM Controller The definition when SCLLBPASS is set to ‘0’ was updated and the SCLPHCAL bit was added (see Register 38-24). The following registers were added: Register 38-31: DDRPHYDLLCTRL: DDR PHY Trim Register Register 38-32: DDRPHYDLLR: DDR PHY DLL Recalibrate Register. Register 38-33: DDRSCLCFG2: DDR SCL Configuration Register 2 Register 38-34: DDRPHYSCLADR: DDR PHY SCL Address Register 41.0 Special Features The Device Configuration Word 0 registers, DEVCFG0/ADEVCFG0, was extensively updated (see Register 41-3). The bit value definitions for the FCKSM<1:0> bits and the POSCMOD<1:0> bits in the Device Configuration Word 1 registers, DEVCFG1/ADEVCFG1, were updated (see Register 41-4). 44.0 Electrical Characteristics Parameter DO50 (COSCO) was removed from the Capacitive Loading Requirements on Output Pins (see Table 44-22).Reason for Change: To Improve ProductivityDate Document Changes Effective: 15 Jan 2018
Microchip has released a new DeviceDoc for the PIC32MZ Graphics (DA) Family Errata of devices.Description of Change: 1) Silicon issue 25. (System Bus) was updated. 2) Added silicon issues 34. (Primary Oscillator), 35. (Primary Oscillator), 36. (Primary Oscillator), 37. (Primary Oscillator), 38. (GPU), 39. (SDHC), 40. (PMP), 41. (I2C), 42. (Crypto), 43. (Crypto), 44. (CTMU), 45. (Timer1), 46. (Timer1), 47. (Timer1), 48. (Timer1), 49. (Timer1), and 50. (Timer1). 3) Added data sheet clarifications -1. (Primary Oscillator)-2. (Primary Oscillator) -3. (Primary Oscillator), 4) (Device Configuration Word 0 Registers (DEVCFG0/ ADEVCFG0).5) (Device Configuration Word 1 Registers (DEVCFG1/ADEVCFG1).Reason for Change: To Improve ProductivityDate Document Changes Effective: 15 Dec 2017NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new DeviceDoc for the PIC32MZ Graphics (DA) Family Datasheet of devices. Notification Status: FinalDescription of Change: 1) Updated the value of pin 168 from “CVREFOUT/AN5/RPB10/RB10” to “AN5/RPB10/RB10” in Table 6, 32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash, 640 KB SRAM, and 32 MB DDR2 SDRAM) with XLP Technology 2) Updated Virtual Address column heading from BF80 to BF82. Updated virtual addresses from 70xx to E0xx for “Parallel Master Port (PMP)”3) Updated resolutions in Key features list on 0 “Graphics LCD (GLCD) Controller”4) Added “eMMC Standard: JESD84-A441” to features list on Secure Digital Host Controller (SDHC)5) Table 44-7, Table 44-8, Table 44-9, Table 44-10, Table 44-11, Table 44-16, Table 44-18 updated various DC Characteristics parameters. Table 44-27, Table 44-28, Table 44-29 updated various AC Characteristics parameters.6) Revision C intro - corrected initial occurrence of VDDR1V8 TO VDD1V8
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